1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly, to a shift register circuit adaptive for use in a liquid crystal display with low frame rate.
2. Description of the Prior Art
Along with the advantages of thin appearance, low power consumption, and low radiation, liquid crystal displays (LCDs) have been widely applied in various electronic products for panel displaying. The operation of a liquid crystal display is featured by modulating voltage drops between opposite sides of a liquid crystal layer for twisting the angles of the liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of light source provided by a backlight module. In general, the liquid crystal display comprises plural pixel units, a shift register circuit, and a source driver. The source driver is utilized for providing plural data signals to be written into the pixel units. The shift register circuit comprises a plurality of shift register stages and functions to generate plural gate signals for controlling the operations of writing the data signals into the pixel units. That is, the shift register circuit is a crucial device for providing a control of writing the data signals into the pixel units.
FIG. 1 is a schematic diagram showing a prior-art shift register circuit. As shown in FIG. 1, the shift register circuit 100 comprises a plurality of shift register stages and, for ease of explanation, illustrates an (N−1)th shift register stage 111, an Nth shift register stage 112 and an (N+1)th shift register stage 113. Each shift register stage is employed to generate one corresponding gate signal furnished to one corresponding gate line based on a first clock CK1 and a second clock CK2 having a phase opposite to the first clock CK1. For instance, the (N−1)th shift register stage 111 is employed to generate a gate signal SGn−1 furnished to a gate line GLn−1, the Nth shift register stage 112 is employed to generate a gate signal SGn furnished to a gate line GLn, and the (N+1)th shift register stage 113 is employed to generate a gate signal SGn+1 furnished to a gate line GLn+1. The Nth shift register stage 112 comprises a pull-up unit 120, an input unit 130, an energy-store unit 125, a discharging unit 140, a pull-down unit 150 and a control unit 160. The pull-up unit 120 pulls up the gate signal SGn according to a driving control voltage VQn. The discharging unit 140 and the pull-down unit 150 are employed to pull down the driving control voltage VQn and the gate signal SGn respectively according to a pull-down control signal Sdn generated by the control unit 160.
In the operation of the shift register circuit 100, when the driving control voltage VQn retains low-level voltage, the gate signal SGn is supposed to continuously hold low-level voltage. However, because of a capacitive coupling effect caused by the device capacitor of the pull-up unit 120, the rising and falling edges of the first clock CK1 have an effect on the driving control voltage VQn and the gate signal SGn. The driving control voltage VQn affected is likely to incur improper operations of the pull-up unit 120, which results in the level drifting phenomena of the gate signal SGn and degrades image display quality.